An important trend in development of semiconductor technology is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) for improving integration level and reducing manufacturing cost. However, it is well known that short channel effects arise as the size of MOSFETs decreases. When the size of the MOSFET is scaled down, a gate of the MOSFET has a smaller effective length and actually controls fewer charges in a depletion region when a gate voltage is applied. Consequently, the MOSFET has a reduced threshold voltage with a reduced channel length.
To suppress the short channel effect, U.S. Pat. No. 6,413,802 discloses a FinFET formed on a SOI substrate, comprising a channel region provided in a central portion of a fin of semiconductive material and source/drain regions provided at two ends of the fin. A gate electrode is provided at both sides of the channel region and surrounds the latter to provide, for example, a double-gate FinFET, in which inversion layers are created at the sides of the channel. The channel region in the fin has a small thickness so that the whole channel region is controlled by the gate, as a result of which, the short channel effect is suppressed.
It is also known that mobility of carriers can be increased by applying a suitable stress to a channel region of the MOSFET, which in turn reduces on-state resistance and increases a switching speed of the device. However, it is difficult in the FinFET to apply the suitable stress to the channel region in a direction between a source region and a drain region. In other words, the strained FinFET is still a challenge.